I. Field of the Disclosure
The technology of the disclosure relates generally to memory bitcells, and particularly to bitcells storing decoded values.
II. Background
Processor-based computer systems include digital circuits that employ memory for data storage. Such memory often contains a plurality of bitcells, wherein each bitcell is able to store a single bit value. Memory may also contain other digital circuits that use encoded words to control access to the bitcells according to a memory address in a received memory access request. One example is use of an encoded word to provide way selection in a cache memory. An encoded word of “n” bits enables a digital circuit to store fewer bits to retain the equivalent value of a decoded word, where the decoded word has 2n-bits. Thus, an n-bit encoded word can be decoded into a “one-hot” decoded word of 2n-bits. A word is “one-hot” when only one bit within the word is at a hot logic level, while the remaining bits in the word are each at a non-hot logic level. As a non-limiting example, a 2-bit encoded word “00” may represent a one-hot, 4-bit decoded word “0001,” where the value “1” represents a hot logic level.
Because an encoded word has fewer bits than its corresponding decoded word, storing an encoded word in memory is effective at minimizing the number of storage elements employed to store the word, thus also minimizing circuit area. For example, while storing an n-bit encoded word requires ‘n’ storage elements, storing an equivalent 2n-bit decoded word would require 2n storage elements. Thus, the area required for storing an encoded word may be less than the area required to store a corresponding decoded word. However, once the encoded word is read from the memory, decoder logic is required to convert the encoded word into a decoded word. Thus, it is common for a digital circuit to read the encoded word from the memory, which is then decoded by a decoder function into a decoded word for use by the circuit.
As an example, FIG. 1 illustrates an exemplary cache memory 10 that stores encoded words for use in memory accesses. As illustrated in FIG. 1, the cache memory 10 includes a plurality of sets 12(0)-12(M−1), wherein ‘M’ is a positive whole number such that the number of the plurality of sets 12 is ‘M’. Each set 12(0)-12(M−1) includes a prediction array 14(0)-14(M−1) that receives a 2-bit encoded word 16(0)-16(M−1) from an encoder 18(0)-18(M−1). Each prediction array 14(0)-14(M−1) is comprised of six transistor (6T) Static Random Access Memory (SRAM) bitcells (not shown) in this example. A decoder 20(0)-20(M−1) is also included in each set 12(0)-12(M−1), wherein the area of the decoder 20(0)-20(M−1) directly correlates to the number of storage elements within the prediction array 14(0)-14(M−1). Further, each set 12(0)-12(M−1) includes a data array 22(0)-22(M−1), wherein each data array 22(0)-22(M−1) is divided into four ways 24(0)-24(3). The way 24 information (not shown) for each set 12(0)-12(M−1) is stored as 2-bit predicted words 26(0)-26(N−1) within each prediction array 14(0)-14(M−1), (wherein ‘N’ is a positive whole number such that the number of the plurality of predicted words 26 is ‘N’).
With continuing reference to FIG. 1, using components relating only to set 12(0) of the cache memory 10 as an example, a 4-bit word 28(0) representing a way 24 within the data array 22(0) of the set 12(0) is provided to the encoder 18(0). The encoder 18(0) converts the 4-bit word 28(0) into the 2-bit encoded word 16(0) prior to providing the way 24 information to the prediction array 14(0). Such a conversion is performed, because the prediction array 14(0) stores the way 24 information associated with the data array 22(0) as a 2-bit encoded word (e.g., the 2-bit predicted word 26(0)) to save storage area within the cache memory 10. Upon receiving the 2-bit encoded word 16(0), the prediction array 14(0) determines which way 24(0)-24(3) to select, and provides the 2-bit predicted word 26(0) to the decoder 20(0). The decoder 20(0) converts the 2-bit predicted word 26(0) into a one-hot, 4-bit decoded word 30(0), wherein the hot bit within the 4-bit decoded word 30(0) represents the way 24 to be selected within the data array 22(0). For instance, a value of “0001” may represent way 24(0), while a value of “1000” may represent way 24(3) of the data array 22(0). Once the 4-bit decoded word 30(0) has been provided to the data array 22(0), data within the selected way 24 may be provided to a cache output 32(0).
As evidenced by this example, the prediction array 14(0) only requires two storage elements for each way 24 entry, because the 2-bit predicted word 26(0) is encoded in 2 bits. However, when reading the 2-bit predicted word 26(0) from the prediction array 14(0), the 2-bit predicted word 26(0) must be decoded into the 4-bit decoded word 30(0) in order to select the desired way 24 in the data array 22(0). Thus, even though the prediction array 14(0) is configured to store 2-bit words rather than 4-bit words in an attempt to save area, the required decode function increases the latency incurred each time the way 24 information is read from the prediction array 14(0).
Moreover, in many applications executed by digital circuits, the read path to read memory is often the critical path. As previously described above, when storing encoded words that represent information such as memory addresses for memory access requests, a decoder is placed within the read path in order to generate the decoded word from the stored encoded word. If the read path is the critical path in memory for memory accesses, the time required to decode the encoded word causes an increase in read latency. Therefore, the overall latency of the memory is increased as a result of decoding the stored encoded word for every read operation.